In general, a signal propagation time period is largely dominated by the resistance of the propagation path and the capacitance applied to the propagation path. Therefore, research and development efforts have been made for reduction in resistance or capacitance so as to implement a semiconductor integrated circuit operable at an ultra high speed. One of the solutions to reduce the capacitance applied to the signal propagation path is to employ airbridge-type metallizations as described in "A HIGH-YIELD GaAs MSI DIGITAL IC PROCESS", IEDM 82, pages 162 to 165.
A typical process sequence of fabricating the airbridge-type metallization is illustrated in FIGS. 1A to 1D. When there are formed active areas for component transistors (not shown) and a first level interconnections (not shown) in a semiconductor substrate 1, a first inter-level insulating film 2 overlies the surface of the semiconductor substrate 1. On the first interlevel insulating layer 2 is deposited a conductive material which is etched and patterned to form second level interconnections 3, 4 and 5. For electrical isolation from the second level interconnections 3 and 5, a second inter-level insulating film 6 is deposited on the second level interconnections 3, 4 and 5, and, then, contact windows 7 and 8 are formed in the second inter-level insulating film 6 to partially expose the top surfaces of the second level interconnections 3 and 5, respectively. The resultant structure of this stage is shown in FIG. 1A.
Subsequently, a temporal pier 9 of polymide is formed on the second inter-level insulating film 6 as shown in FIG. 1B, and a conductive material of gold is deposited by using a plating technique to form a conductive strip serving as a third level interconnection 10 which is conformal to the upper surface of the structure. The third level interconnection 10 is connected at one end thereof to the second level interconnection 3 and at the other end thereof to the second level interconnection 5 as shown in FIG. 1C, then the second level interconnection 3 is electrically coupled to the second level interconnection 5 through the third level interconnection 10.
Finally, the temporal pier 9 is removed by using an isotropic etching technique, so that the third level interconnection 10 is spaced apart from the second inter-level insulating film 6, and a hollow space 11 is formed between the third level interconnection 10 and the second inter-level insulating film 6. This results in that the third level interconnection 10 becomes an airbridge-type interconnection.
The central portion of the third level interconnection 10 is not physically contact with the second inter-level isolating film 6, so that the parasitic capacitance is drastically decreased. However, a problem is encountered in the prior-art semiconductor device with the airbridge-type interconnections in that some of the airbridge-type interconnections tend to be crushed during wafer separation process. Namely, after a resilient sheet is bonded to the wafer, the wafer is gently rubbed with a rubber roller to deepen the scribing lines, then stretching the resilient sheet for separation of the semiconductor chips. When the wafer is of the gallium arsenide, the wafer has a thickness of about 350 microns after grinding the back surface of the wafer because of the brittleness. Then, the rubbing step is carried out for perfect separation. As a result, the airbridge-type interconnection is subjected to a pressing force due to the rubbing. This results in deterioration in reliability due to disconnection and in increasing in the parasitic capacitance due to physical contact with the second inter-level insulating film 6. The reason why some of the airbridge interconnections are crushed is that a force concentrates on the central portion of each airbridge-type interconnection 10 because the central portion is higher than the other portions by some microns.